Parallel Design vs Modules: Essential Solutions for High-Power Semiconductor Applications
Why Power Devices Need Parallel Design in Renewable Energy
With the rapid development of renewable energy technology, the demand for high-power semiconductor devices continues to increase. Particularly in renewable energy sectors, there’s a need for power devices capable of handling enormous currents. However, due to production cost limitations, technical difficulties, and market demand factors, single high-power semiconductor devices often struggle to meet these application requirements. Therefore, parallel design of high-power IGBTs and SiC MOSFETs has become an effective solution.This article introduces key points of parallel design and recommends several corresponding products from onsemi.
Why Is Parallel Design Necessary for Power Devices?
In high-power scenarios like solar and wind power generation, power devices need to handle extremely large currents. Power semiconductor manufacturers typically don’t produce devices with very high current ratings because:
- Large-size chips have lower production yields
- Insufficient market demand
- Larger packaging dimensions for high-current chips can lead to increased package warping issues
The industry’s common approach is to connect multiple devices with smaller current ratings in parallel. This not only meets high current demands but also reduces conduction losses, improves efficiency, and expands current capacity.
However, in practical parallel design applications, several challenges often arise:
- Uneven current distribution during conduction
- Uneven current during switching
- Gate oscillation between chips
Addressing Current Imbalance During Conduction
In the conduction process of parallel power devices, ensuring uniform current distribution is a critical consideration, often affected by multiple factors leading to current imbalance. The primary factor isinconsistency in Vce(sat) and RDS(on) between devices during conduction. When some devices exhibit lower Vce(sat) or RDS(on), they naturally tend to carry more current, disrupting the ideal current balance. Additionally,differences in threshold voltage (Vgs(e)th)also cause uneven current distribution—devices with smaller Vgs(e)th have smaller conduction resistance (RDS(on)), further aggravating current imbalance. Furthermore,temperature characteristics of devicescannot be ignored; negative temperature coefficients may cause more uneven current distribution as temperature rises, while positive temperature coefficients help improve current balancing.
To effectively solve static current balancing issues, we need to consider both device selection and system design.
First, in device selection, it’s recommended to screen conduction impedance at nominal operating current to ensure impedance matching between parallel devices, achieving more uniform current distribution. It’s advisable to prioritize power devices with consistent or similar Vce(sat) and RDS(on) parameters, ensuring these parameter differences are controlled within 0.1V and 5% respectively.
Second, differences in Vgs(e)th parameters between different devices should be controlled below 0.1V. Finally, adopting power semiconductor devices with positive temperature coefficients (PTC) is a wise choice for improving current balance, as PTC characteristics allow devices to automatically adjust current distribution with rising temperature, favoring equilibrium. However, if the application requires low switching frequency and considers using IGBTs with negative temperature coefficients (NTC) to optimize conduction losses, ensure that the operating current exceeds the NTC inflection point to avoid worsening current imbalance caused by temperature.
Managing Switching Current Imbalance
During the switching phase of power semiconductor devices, dynamic current imbalance issues are particularly prominent.This phenomenon is partly attributed to inconsistencies in key parameters between devices, such as differences in VTH, Miller plateau voltage (Vplateau), and input capacitance (Cies).Devices with lower VTH conduct earlier due to their lower threshold voltage, and because of their smaller Cies and gate-emitter capacitance (Cge), they charge faster, causing these devices to bear greater energy losses (Eon and Eoff) during switching actions. This concentration of energy loss leads to increased junction temperature (TJ), which may further reduce VTH, making these devices conduct even earlier in subsequent switching actions, forming a cycle of current concentration that exacerbates current imbalance.
Additionally,larger source inductance and impedance cause slower device turn-on and turn-off delays. Specifically, smaller source parasitic inductance (LS) leads to devices bearing larger energy losses (Eon) during turn-on, while larger source parasitic inductance causes devices to bear greater energy losses (Eoff) during turn-off. This imbalance caused by circuit layout results in excessive current in some devices during the switching process while others carry less current, creating current imbalance.
Therefore, to solve switching current imbalance issues, comprehensive consideration and optimization from both the device’selectrical characteristicsandlayoutaspects are necessary. First, conduct detailed screening and sorting of the gate-emitter Vgs(e)th of power devices at nominal operating current, ensuring that the Vgs(e)th difference between devices is controlled within 0.1V, which helps achieve more consistent switching behavior. Second, to balance current, ensure consistent loop length between each power device and gate driver, helping reduce switching time inconsistencies caused by loop differences. Finally, symmetrical parasitic inductance design is equally important; in circuit layout, ensure that the parasitic inductance from the power device’s source or emitter to the driver IC is symmetrical and as equal as possible.
Preventing Gate Oscillation Between Chips
Gate oscillation issues stem from differences in connections between chips and external circuits when power devices are used in parallel, whichtogether may trigger L-C resonance. Specifically, each chip carries parasitic input capacitances Cgd and Cgs; when parasitic inductance exists in the common gate and source between chips, L-C resonance may occur between chips. Additionally, small differences in chip parameters, such as different threshold voltages Vgs(th), and different parasitic inductances between the source and driver in external connections, may also contribute to this resonance. If the circuit lacks sufficient impedance to dissipate this energy, resonance occurs, causing oscillation in the gate voltage Vgs.
This oscillation not only increases the switching losses of power devices but may also cause repeated switching, potentially damaging power devices due to excessive losses over time. Therefore, to reduce the risk of gate oscillation, design considerations should include matching parasitic inductance between chips, ensuring that the parasitic inductance between the Source and Drain of parallel chips (such as LD1 and LD2, LS1 and LS2, LG1 and LG2 in the above figure) are equal or as close as possible to reduce L-C resonance caused by inductance mismatch. If the chip’s internal gate resistance is zero ohms or very low, configure external gate resistors (Rg) separately for each device. This helps dissipate energy generated by L-C resonance, reducing gate oscillation.
Single Device Parallel or Module: Making the Right Choice in Design
In high-power applications, the choice between paralleling single devices or using modules should comprehensively consider factors like cost, power consumption, and installation convenience. As a global leading supplier of power semiconductor devices, onsemi’s product line covers a wide range of options designed to meet power management needs in different application scenarios. In power device selection, whether pursuing ultimate efficiency with single-device solutions or highly integrated, optimized thermal module designs, onsemi can provide satisfactory choices. Onsemi’s product lineup offers a full range of high, medium, and low voltage power discrete devices and advanced power module solutions, including IGBTs, MOSFETs, SiC, Si/SiC hybrid modules, diodes, SiC diodes, and intelligent power modules (IPM).
Onsemi has newly launched theM3S 1200V EliteSiC Power Integrated Module, which offers a comprehensive and rich product portfolio with output power flexibly scalable from 25kW to 100kW. This solution is particularly suitable for electric vehicle DC ultra-fast charging stations and battery energy storage systems (BESS), providing high-efficiency power solutions to meet different needs.
The 1200V SPM31 Intelligent Power Module (IPM)using 7th generation (FS7) Insulated Gate Bipolar Transistor (IGBT) technology offers higher efficiency, smaller size, and higher power density compared to other leading solutions in the market, resulting in lower overall system costs. Because these IPMs integrate optimized IGBTs, achieving higher efficiency, they are particularly suitable for three-phase variable frequency drive applications such as heat pumps, commercial HVAC systems, and industrial pumps and fans.
