Cadence Acquires Arm’s Artisan IP: Bolstering Chiplet and 3D IC Capabilities for Next-Gen Computing

Strategic Acquisition Expands Foundation IP Portfolio

In a significant industry move, Cadence Design Systems has announced a definitive agreement to acquire Arm’s Artisan Foundation IP business. The acquisition strategically positions Cadence to enter the foundation IP market while supporting its ambitious plans in AI and chiplet-based design.

The deal brings critical components under Cadence’s umbrella, including standard cell libraries, memory compilers, and GPIOs—all essential building blocks for advanced node SoCs and modular chip architectures. This acquisition not only expands Cadence’s IP portfolio but also brings aboard a seasoned engineering team with expertise in chiplet enablement.

“With the addition of Arm’s Artisan IP, Cadence will enter the foundation IP market and support new growth across design services and chiplet offerings,” explained Boyd Phelps, Senior Vice President and General Manager of the silicon solutions group at Cadence.

The Shift to Multi-Die Architectures

According to Alok Jain, Corporate Vice President of R&D at Cadence Design Systems India, the semiconductor industry is rapidly moving away from traditional monolithic SoCs toward multi-die, multi-node architectures.

“3D ICs and chiplets are no longer theoretical; they are production-ready,” Jain emphasized in an exclusive conversation with EE Times. He pointed to Intel’s Meteor Lake as a real-world example of chiplet deployment—manufactured using multiple foundries and process nodes.

To address this paradigm shift, Cadence has developed an integrated 3D IC platform that combines design tools (Virtuoso), packaging solutions (Allegro), and comprehensive thermal and electromagnetic analysis capabilities. The company is actively collaborating with major foundries including TSMC and Intel Foundry to certify and enable these complex 3D IC designs.

The main challenges in chiplet-based design—increased complexity, effective partitioning, and managing thermal and electromagnetic interactions—are being tackled through partnerships with outsourced semiconductor assembly and test providers to develop robust thermal solutions and ensure manufacturability.

AI-Driven Transformation of Chip Design

Beyond architectural innovations, Cadence is revolutionizing the chip design workflow itself through artificial intelligence. The company’s AI strategy encompasses both optimization AI for improving iterative processes and agentic AI for enabling autonomous design decisions.

“Every EDA tool is iterative by nature; AI can make each iteration smarter—faster, more productive, and more performance-oriented,” Jain explained. The company has already launched five AI platforms, with more in development, progressing through different levels of autonomy.

“We are starting with Levels 1 and 2 of agentic AI, where a human is still in the loop. The ultimate goal—Level 5—is fully autonomous design, verification, and implementation,” he added.

Rather than replacing engineers, Cadence’s AI vision aims to augment human decision-making by refining options and validating outcomes. Teams are exploring innovative applications of large language models to mine engineering documentation and bug repositories, enabling natural language interfaces across the design workflow.

“The idea is to embed some form of chat into every Cadence tool, allowing users to engage in natural dialogue to understand and use the tools more effectively,” said Jain.

India: From Support Center to Innovation Hub

Since establishing a base in India in 1987, Cadence has evolved its presence from a support center to a critical innovation hub. Today, the country houses large R&D teams that play a vital role in developing design and verification IPs, increasingly leveraging AI and ML techniques.

“India is what I call a microcosm of the entire Cadence,” Jain noted. “We have nearly every corporate function represented here. India is actively participating in this AI evolution.”

The company is also addressing the talent pipeline through its collaboration with the India Council for Technical Education, reforming VLSI curriculum across more than 120 Indian institutions. Through its Academic Network, Cadence provides over 350 institutions in India with hands-on access to industry-grade tools.

Furthermore, Cadence is nurturing the startup ecosystem by making its tools accessible to chip design startups and incubators through government-backed initiatives such as Chips-to-Startup.

Future Outlook: Innovation Meets Promotion

When asked about balancing promotion and innovation, Jain offered a clear perspective: “The answer is both. We are constantly innovating—AI, chiplets, IP—and we are actively promoting that innovation with our customers. One cannot exist without the other.”

With the Artisan acquisition, Cadence is positioning itself at the forefront of the chiplet revolution while building a comprehensive foundation for the future of semiconductor design. As the industry continues its transition to more modular, heterogeneous computing architectures, Cadence’s expanded capabilities in foundation IP, design tools, and AI-driven workflows provide a compelling vision for addressing the challenges of next-generation chip design.